This application is related to Japanese application No. 2000-94339 filed on Mar. 30, 2000, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, a method of reading from and writing to the same, and a method of manufacturing the same. More particularly, it relates to a nonvolatile semiconductor memory having cells of split gate (SPG) structure and being capable of high integration, a method of reading from and writing to the same, and a method of manufacturing the same.
2. Description of Related Art
Virtual grounding structure has been proposed with a view to reducing the size of memory cells in a nonvolatile semiconductor memory,. In the virtual grounding structure, one bit line can be omitted, because a bit line does not need to contact an impurity diffusion layer which functions as a drain, and a source of a cell can serve as a drain of another cell adjacent to the cell so that one bit line can be omitted. Therefore, scaling of the cells is easily performed and an area of the cells can be minimized in NOR structures. Thus, the virtual grounding structure is suited to realize large capacity. An example of a conventional virtual grounding structure is described in Japanese Unexamined Patent Publication No. HEI 6 (1994)-196711. Now referring to FIG. 22, the conventional technique is explained.
In FIG. 22, a buried bit line 51 in a semiconductor substrate 50 of the first conductivity type is asymmetrically constituted of a low concentration impurity diffusion layer 52 of the second conductivity type and a high concentration impurity diffusion layer 53 of the second conductivity type. The impurity diffusion layer 52 overlaps with a floating gate 54a of an adjacent memory cell and the impurity diffusion layer 53 overlaps with a floating gate 54b of another adjacent memory cell. That is, the buried bit line 51 serves as a source of a cell and a drain of a cell adjacent to the cell.
However, in the above-mentioned virtual grounding structure, it is known that data reading from a cell is often interfered by a cell adjacent to the cell. Accordingly, it has been difficult to achieve satisfactory reading precision and to obtain a multi-valued circuit.
Regarding this drawback, a virtual grounding structure with SPG cells has been known (Japanese Unexamined Patent Publication No. HEI 5 (1993)-152579). Specifically, as shown in FIG. 23, floating gates 62a and 62b are provided as sidewall spacers on the sidewalls of a SPG 61 in the channel direction, respectively and a control gate 63 is provided along the channel direction. Further, an impurity diffusion layer 65a which is capacitively coupled with the floating gate 62a and an impurity diffusion layer 65b which is capacitively coupled with the floating gate 62b and the SPG 61 are formed in a surface layer of a semiconductor substrate 64. The impurity diffusion layer 65b is also coupled capacitively with the floating gate 62a of an adjacent cell.
Various methods of rewriting the memory cells have been known, for example, a method of injecting electrons from the substrate to the floating gate or from the floating gate to the drain with use of Fowler-Nordheim (FN) tunnel current, and a method of injecting electrons from the source to the floating gate or from the drain to the floating gate with use of channel hot electrons (CHE). In the memory cell constituted as shown in FIG. 23, rewriting is not performed by the method of injecting the electrons from the floating gate to the drain with use of the FN tunnel current since the floating gates are formed on both sidewalls of the SPG. Therefore, the applicable range of the memory cell of such a construction is limited.
Further, if the memory is more miniaturized and the gate is formed shorter, dielectric strength between the source and the drain is reduced and writing errors are resulted. Accordingly the reduction of the cell area is difficult.
FIG. 24(a) is a plan view for illustrating the difficulty in reducing the cell area by the conventional technique described above. FIGS. 24(b) and 24(c) are cross-sections cut along the lines A-Axe2x80x2 and B-Bxe2x80x2 shown in FIG. 24(a), respectively. In FIGS. 24(a) to 24(c), reference numeral 71 signifies a diffused bit line, 72 a low concentration impurity diffusion layer, 73 a high concentration impurity diffusion layer, 74 a floating gate, and 75 a control gate. FIG. 24(b) is a cross section in the direction parallel to the control gate and FIG. 24(c) is a cross section in the direction vertical to the control gate.
When the nonvolatile semiconductor memory shown FIG. 24(a) to 24(c) is formed, provided that the minimum manufacturing order of the nonvolatile semiconductor memory is F (e.g., if the manufacture is under 0.15 xcexcm process, F=0.15 xcexcm), the size of the memory cell in the direction parallel to the control gate will be Lg (channel length between the source and the drain)+F (bit line width).
In this memory cell, when a common writing voltage is applied to an adjacent bit line, the value Lg of about 0.3 xcexcm is required to ensure dielectric strength between the source and the drain. That is, when the minimum manufacturing order F is 0.15 xcexcm, Lg=2F is established. As a result, the size of the memory cell in the X direction (horizontal to the control gate) will be 3F. The size in the Y direction (vertical to the control gate) will be 2F, which is the sum of the size F of a portion where the floating gate and the control gate overlaps with each other and the size F of a portion between the memory cells.
Thus, the memory cell area in the virtual grounding structure according to the prior art is 6F2. The actual minimum area 4F2 is difficult to realize by the prior art technique.
Also in the structure shown in FIG. 23, an additional transistor (a SPG transistor) is required between the source and the drain, so that the area occupied by the transistor has been an obstacle to the scaling.
Since such a SPG region inevitably exists as long as the SPG cells are employed, the cell area of 4F2, which is the actual minimum value, is difficult to realize as in the previously mentioned structure.
According to the present invention, provided is a nonvolatile semiconductor memory including at least two cells each comprising:
a floating gate formed on a semiconductor substrate with the intervention of a first insulating film;
a split gate (SPG) formed on the semiconductor substrate with the intervention of a second insulating film at a predetermined distance from the floating gate;
a control gate formed at least on the floating gate with the intervention of a third insulating film; and
an impurity diffusion layer formed in a surface layer of the semiconductor substrate and capacitively coupled with an edge of the floating gate on an opposite side to the SPG in the channel direction,
wherein the floating gate and the SPG of one cell are alternately arranged with the floating gate and the SPG of another adjacent cell along the channel direction and the impurity diffusion layer of one cell is capacitively coupled with a SPG of another adjacent cell.
The present invention further provides a method of reading data from the above-described nonvolatile semiconductor memory, wherein the data reading from one cell is performed by grounding the impurity diffusion layer of said one cell and applying a voltage to an impurity diffusion layer of another adjacent cell, or by applying a voltage to the impurity diffusion layer of said one cell and grounding the impurity diffusion layer of said another adjacent cell.
Still further, according to the present invention, provided is a method of reading data from the above-described nonvolatile semiconductor memory, wherein the data reading from one cell is performed by applying a voltage to the SPG of said one cell and avoiding voltage application to a SPG of another adjacent cell to isolate said one cell from said another adjacent cell.
Still further, according to the present invention, provided is a method of writing/erasing data to/from the above-described nonvolatile semiconductor memory, wherein the data writing/erasing is performed by utilizing FN tunnel current flowing between the floating gate and the semiconductor substrate or the floating gate and the impurity diffusion layer of one cell.
Still further, according to the present invention, provided is a method of writing data to the above-described nonvolatile semiconductor memory, wherein the data writing to one cell is performed by applying a predetermined voltage to the impurity diffusion layer of said one cell and grounding an impurity diffusion layer of another cell to flow electric current, and applying a first voltage to the SPG to weakly invert a channel region facing the SPG to inject hot electrons from an edge of the SPG.
Still further, according to the present invention, provided is a method of data writing to the above-described nonvolatile semiconductor memory, wherein the data writing to one cell is performed by applying a predetermined voltage to the impurity diffusion layer of said one cell and grounding an impurity diffusion layer of another cell to flow electric current, and applying a second voltage to the SPG to strongly invert a channel region facing the SPG to inject hot electrons from the impurity diffusion layer of said one cell.
Still further, according to the present invention, provided is a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
(a1) forming at least two floating gates for providing at least two cells on a semiconductor substrate with the intervention of a first insulating film to have a predetermined distance therebetween in a channel direction;
(b1) forming two SPGs on the semiconductor substrate with the intervention of a second insulating film at one side of each of the floating gates along the channel direction;
(c1) forming an impurity diffusion layer in a surface layer of the semiconductor substrate between the floating gate of one cell and the SPG of another adjacent cell so that the impurity diffusion layer is capacitively coupled with the floating gate of said one cell and the SPG of said another adjacent cell; and
(d1) forming a control gate on each of the floating gates with the intervention of a third insulating film.
Still further, according to the present invention, provided is a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
(a2) forming at least two floating gates for providing at least two cells on a semiconductor substrate with the intervention of a first insulating film to have a predetermined distance therebetween in a channel direction;
(b2) performing oblique ion implantation of impurities using the floating gates as a mask or using a mask formed on the floating gates to form an impurity diffusion layer in a surface layer of the semiconductor substrate at one side of each of the floating gates;
(c2) forming two trenches in the semiconductor substrate including a part of the impurity diffusion layer using the floating gates as a mask or using a mask formed on the floating gates;
(d2) forming a second insulating film on the sidewalls and the bottom of the trenches;
(e2) forming two SPGs by burying a conductive material in the trenches; and
(f2) forming a control gate on each of the floating gates with the intervention of a third insulating film.
Still further, according to the present invention, provided is a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
(a2) forming at least two floating gates for providing at least two cells on a semiconductor substrate with the intervention of a first insulating film to have a predetermined distance therebetween in a channel direction;
(b2) performing oblique ion implantation of impurities using the floating gates as a mask or using a mask formed on the floating gates to form an impurity diffusion layer in a surface layer of the semiconductor substrate at one side of each of the floating gates;
(c2)xe2x80x2 forming sidewall spacers on sidewalls of each of the floating gates and forming two trenches in the semiconductor substrate including a part of the impurity diffusion layer using the floating gates and the sidewall spacers as a mask;
(d2) forming a second insulating film on the sidewalls and the bottom of the trenches;
(e2) forming two split gates by burying a conductive material in the trenches; and
(f2) forming a control gate on each of the floating gates with the intervention of a third insulating film.
Still further, according to the present invention, provided is a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
(a2) forming at least two floating gates for providing at least two cells on a semiconductor substrate with the intervention of a first insulating film to have a predetermined distance therebetween in a channel direction;
(b2)xe2x80x3 performing ion implantation of impurities at least to regions between the floating gates using the floating gates as a mask or using a mask formed on the floating gates and annealing;
(c2)xe2x80x3 forming sidewall spacers on sidewalls of each of the floating gates and forming two trenches using the floating gates and the sidewall spacers as a mask to provide a floating impurity diffusion layer and an impurity diffusion layer in a surface layer of the semiconductor substrate under each of the sidewall spacers;
(d2) forming a second insulating film on the sidewalls and the bottom of the trenches;
(e2) forming two SPGs by burying a conductive material in the trenches; and
(f2) forming a control gate on each of the floating gates with the intervention of a third insulating film.
Still further, according to the present invention, provided is a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
(a2) forming at least two floating gates for providing at least two cells on a semiconductor substrate with the intervention of a first insulating film to have a predetermined distance therebetween in a channel direction;
(b2)xe2x80x3 performing ion implantation of impurities at least to regions between the floating gates using the floating gates as a mask or using a mask formed on the floating gates and annealing;
(c2)xe2x80x2xe2x80x3 forming two trenches at least between the floating gates to provide a floating impurity diffusion layer and an impurity diffusion layer below edge portions of the floating gates extending along the sides of the trench, respectively;
(d2) forming a second insulating film on the sidewalls and the bottom of the trenches;
(e2) forming two SPGs by burying a conductive material in the trenches; and
(f2) forming a control gate on each of the floating gates with the intervention of a third insulating film.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.